PERFORMANCE INVESTIGATION ON VLSI ADDERS TO REDUCE POWER AND DELAY

Abstract

The Parallel Prefix Adder (PPA) is considered to be one among the emerging techniques to reduce
the speed of the DSP processor when performing addition operation. There are several research
methodologies available for designing PPA. In this project, we designed an efficient low
implementation of Kogge-Stone prefix adder that is the rapid adder when compared to other PPA.
The PPA follows the multi-bit carry- propagate addition of two input bits. Based on this propagation
mechanism, the interconnection complexity is significantly reduced and also delay optimization can
also be carried between the intermediate paths. The software implementation of the 32-bit Kogge
Stone adder is done in Altera Quartus II 9.1. The presented adder architecture is implemented in both
90nm and 65nm CMOS technologies and parameters like area, power and delay are analysed and
measured.