DESIGN OF XA MODULE USING RNB IN DOMINO LOGIC

Abstract

A replacement VLSI implementation for a finite field multiplier using reordered normal basis is
presented. The hardware architecture uses domino logic building blocks also as True Single Phase
Clock (TSPC) flip-flops to realize exceptional performance. The multiplier has been realized during
a 0.18 µm CMOS process and may perform multiplication correctly up to a clock rate of 1.789 GHz,
requiring 62048 µm2 of silicon area. Compared to similar implementations, the new design yields a
43% reduction in area utilization, and a 12% increase in maximum operating speed. the dimensions
of the multiplier, 233, is suggested by the National Institute of ordinary and Technology (NIST) for
elliptic key cryptography. Finite field multipliers like the proposed one have applications publicly
key cryptography for constrained devices like smart cards or hand-held devices.