Investigation on Variable Latency Speculative Approach in Parallel Prefix Adders

Abstract

In many digital circuits, adders are the most important block. The entire performance of the circuit is
influenced by the characterization of the adder circuit. The conventional adders such as carry
lookahead adder, ripple carry adder, etc., produce huge amount of path delay in the intermediate
stage of computation. This problem can be solved by developing the approximation adders. The
variable latency adder is one of the approximation adders which have the inbuilt error detection and
correction scheme. Prefix computation is the part of the VLSA which is performed by parallel prefix
adders. In this paper, we performed an efficient FPGA implementation of parallel prefix adders such
as Sklansky, Kogge-Stone, Han-Carlson and Ladner Fisher adders. The performance of the above
adders are analyzed and Kogge Stone adder performed 89% better than Sklansky adder, 50% better
than han carlson and 66.6% better than Ladner Fisher adder.