Area Efficient Carry Select Adder Using Parallel Prefix Adder Structure
Adders are the basic building blocks of modern digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. The prerequisite ofthe adder is that, it is primarily fast and secondarily efficient in terms of power consumption and chip area.
A Conventional Carry Select Adder has two Ripple Carry Adder (RCA) which consists of cascaded of “N” single bit full adders. Output carry of previous adder becomes the input carry of next full adder and so on. Therefore, the carry of this adder traverses longest path called worst case delay path through N stages. Now as the value of N increases, delay of adder will also increase in a linear way.
The proposed Carry Select Adder structure which adopts modified parallel prefix adder at the upper part and Binary to Excess-1 convertor at the lower part of a design. This adder is being compared with Conventional CSA and Carry Select Adder using Parallel Prefix Adder in terms of area and performance. The simulations and synthesis of the proposed adder are done using Verilog HDL in XILINX ISE.