Analysis Of Power Leakage Controlling In 7t Sram Cell Using Self-Controlling Technique For High Security Data Transformation

  • Vamshi Krishna Kambhampati, Dr. Ram Gopal, Dr. P. A. Abdul Saleem


 In Today's Digital Era, Any Integrated Device's Memory Is An Unavoidable Component. It Also Significantly Increases The Overall Circuit Capacity. Nanotechnology Is Attracting Chip Manufacturers' Attention As The Market For Handheld Devices Grows. Portable Devices With Static Random Access Memory, On The Other Hand, Experience A Power Drain. Leakage Capacity Becomes More Important Than Complex Power Usage As Technology Advances. As A Result, In Our Proposed Sram Memory, We Used The Power Gating Strategy To Reduce Power Consumption, Which Is A Requirement Of The Day. To Reduce Leakage Capacity, We've Added A New Function. Because Of The Leakage Current In Both Pmos And Nmos With Similar Part Sizes. The Move Semiconductors Of Sram Cells Are Replaced With Pmos Rather Than Nmos To Further Reduce Leakage Power Consumption.