Design of Hybrid RISC Processor for Code Compression

Abstract

This investigation utilizes compiler techniques for diminishing memory needed for running and loading program executables. Based on economic incentives, embedded system needs to reduce ROM and RAM is extremely stronger, compiler cost size is also increasing significantly. Alike of network and mobile based computing, the necessity of transmitting an executable code is before placing it to a premium code size. This work concentrates on compressing programmable code size with Hybrid Huffman Code compression and Look up Table with cost minimization. It helps to combine and recognize repeated instruction sequences. In contrary to other approaches, this hybrid method maintains competency to execute programs directly devoid of any intervention in decompression stage. This method is merging with industrial strength for optimizing compiler which facilitates users to provide interaction among conventional code optimization approaches and code compression techniques. It is contended with various complexity associated with optimizing code. The foremost contribution of this investigation is code compression in RISC architecture which is a most resourceful factor for enhancing code compression with repeated code fragments and newer form of hybridized code compression that diminishes cost wise penalty while performing compression.