Ultra-Low-Power Functional VLSI Chip Using Mirror-Amplifier

  • Rishikesh Kumar Thakur

Abstract

Device density in VLSI today enforces the process of chip designing much more complex; whereas MAGIC CAD tools made the IC design in this work, comparatively easier. Study on various amplifiers for sensor applications showed that their powers ranged from a few milliamperes to a few hundred milliamperes at the submicron fabrication processes by MOSIS, but within the affordable cost. Objectives of lowering the power at least by 1000 times in those fabrication processes engaged this research towards completing a new design, called the mirror-amplifier. This design is verified for precise functional behavior for the sensor and total power consumption, using MAGIC extractor and PSPICE electrical simulation tools. A compact model chip layout made silicon area more efficient for MOSIS tiny-chip fabrication in 0.6µm processes. To make even more economical, a multi-die placement technique was applied to the chip layout for this tiny-chip in silicon area of 1500µmX1500µm. MOSIS design rules for multi-die fabrication was verified for process scribe-lines and die packaging. This paper presents details of the key research works, results, completed chip layout and packaging of the chip.

Published
2020-12-31
Section
Articles