Nano-Power Sensor Applications in VLSI Multi-Die Tiny Chip
Abstract
Semiconductor integration has improved over the years by increasing device switching speed and device density, causing increased power consumption and dissipation; therefore, the issues has been considered and improved here. Previously designed VLSI mirror-amplifier had power dissipation of 8.41 milliwatts in CMOS 0.5µm process. Latter the technique was re-applied in this work to completed characterization of each pin signal functions with biasing steps to determine accuracy at the low power response of the IC in order to improve the total power consumption. Signal pin orientation in the simulation and choosing the correct biasing point in two steps proved to be correct procedure to improve. Supply voltage was considered as 3V for the MOSIS process technology. Latest MAGIC layout CAD tools were used for design, and PSPICE was used for simulation and electrical characterization with the help of MAGIC layout extraction tool. Keeping the process and scaling unchanged at 0.5µm as the previous design, the new VLSI design yielded the power dissipation of 4.39 nanowatts in 2nd step by reducing the dynamic loss. The electrical characterizations also confirmed that the chip precisely senses ultra-high-Z signals at inputs for this application. Multi-die chip placement is done for fabrication and also made the final product less expensive by the in-house custom designed pad-frame. This paper presents details of the key research works, results, completed chip layout and applications of the chip.
