Design And Implementation Of A Power Efficient Vedic Multiplier

Abstract

The ever-increasing demand in enhancing the ability of processors to handle the complex and
challenging processes has resulted in the integration of a number of processor cores into one chip.
Still the load on the processor is not less in generic system. This burden can be minimized by boosting
the primary processor with Co-Processors, which are implemented to work on particular functions
like arithmetic computation, Digital Signal Processing, Graphics etc. The speed of ALU majorly
depends on the multiplier.
The research has established and analyzed that Nikhilam Navatashcaramam Dashatah Sutra is the
most effective Sutra, which gives the minimum of delay for multiplication of all the types of short and
long numbers. Further, Nikhilam Navatashcaramam Dashatah Sutra multiplication and
implementation of the Verilog HDL coding is done using Xilinx Tool.