Implementaion of RISC Processor on FPGA

  • Sanket Timane, S.A. Badarkhe, Gaurav Suryawanshi, Mahendra Tayade

Abstract

RISC (Reduced Instruction Set Computer) is a design methodology which supports small and simple set of instructions that all requires the same amount of time to get execute. The proposed processor been carried out with the  Harvard Architecture which use separate storage and signal pathways for instructions and data whereas in the other architecture by Von Neumann architecture ,has only one shared memory for instruction and data with one data bus and address bus with between data memory and process memory.. The RISC processor consists of different blocks such as ALU, control unit (controller), register files and data memory unit. In RISC processor, the one instruction per clock cycle is provisioned. Xilinx ISE design suite is used to implement and analyze 16 bit RISC processor on FPGA.

Published
2020-07-01