Application of Vedic Mathematics in Multipliers

Abstract

Vedic mathematics is the name given to the ancient Indian system of mathematics based on Vedic sutras. Vedic multiplier is based on these Vedic Sutras. The proposed multiplier which uses the concepts of Vedic Mathematics is designed to reduce delay, design complexity, increase speed as well as to decrease power consumption in comparison to conventional multipliers. The project is about high speed Vedic multiplier architecture which is quite different from the Conventional multiplier. A multiplier is an important element in DSP systems, which acts as a building block in most computational digital systems, therefore, speed and power consumption are two important parameters of design.  The Vedic Multiplier computed the partial products in a simultaneous manner and the carry was propagated using adders. The high speed multipliers are needed in DSP applications for fast execution. Therefore in this project we implement a 4*4 bit multiplier using Urdhava Tiryagbhyam algorithm using VHDL coding and the output is observed on FPGA kit(Spartan 3E).