Low Power Resource Efficient Ternary Content Addressable Memory Using Multiport SRAM

Abstract

A Ternary Content addressable memory (TCAM) performs search operation by comparing input string with the stored data at high speed. TCAM is popular in high speed packet classification, forwarding and network switches. TCAM functionality is emulated with SRAM to overcome the limitations of TCAM such as small storage quantity, complex memory structure and high energy consumption. Resource Efficient SRAM based TCAM (REST) architecture utilize the functionalities of TCAM using optimal resource. The low power REST architecture has been proposed with 72X28 multiport SRAM to improve the speed and to reduce the power consumption of TCAM. In this proposed architecture, the virtual blocks of multiport SRAM unit is used to store the address information given in the TCAM. A72x28 low power REST architecture is simulated using modelsim and Xilinx Vivado.