M Durga Prakash, B V V Satyanarayana,. “Gate Oxide Overlapped Heterojunction Tunneling Transistor Based Low Power SRAM Cell Topologies”. International Journal of Advanced Science and Technology 29, no. 3 (March 3, 2020): 4319 - 4329. Accessed May 2, 2024. http://sersc.org/journals/index.php/IJAST/article/view/5257.