Govardhani. Immadi, M. Venkata Narayana, A. Sree Madhuri, D. Bhavya Sree, V. S. Charmila, W. Rachana, “Design and Implementation of High Speed Parallel Cyclic Redundancy Check-32 Bit Using Verilog”, IJAST, vol. 29, no. 05, pp. 9897 - 9903, May 2020.