M Durga Prakash, B. V. V. S. (2020) “Gate Oxide overlapped Heterojunction Tunneling Transistor based Low Power SRAM Cell Topologies”, International Journal of Advanced Science and Technology, 29(3), pp. 4319 - 4329. Available at: http://sersc.org/journals/index.php/IJAST/article/view/5257 (Accessed: 2May2024).