Govardhani. Immadi, M. Venkata Narayana, A. Sree Madhuri, D. Bhavya Sree, V. S. Charmila, W. Rachana (2020) “Design and Implementation of High Speed Parallel Cyclic Redundancy Check-32 Bit Using Verilog”, International Journal of Advanced Science and Technology, 29(05), pp. 9897 - 9903. Available at: http://sersc.org/journals/index.php/IJAST/article/view/19468 (Accessed: 5May2024).