Low Power – Area Efficient Multiplexer Restructuring for VLSI Implementation - M. Sathish, B. Samiksha (International Journal of Advanced Science and Technology, 2019)
The area of logic is attracting much attention of researchers at the present time. Logic concept of digital circuit designing is getting hold of wide scope in the area of nanotechnology, quantum computing, signal processing, optical computing etc due to its capability to design low power loss digital circuits. In this paper a noble MUX is proposed. Various classical operations by this proposed gate are shown here. This paper also proposes 2:1 MUX, 4:1 MUX, 8:1 MUX and the design for FPGA architecture. Technology mapping optimizations that target the proposed architectures are also perform within Xilinx software. Both for complex logic block and routing area while maintaining mapping depth, the nominated architecture of this paper analyze the logic size, area and power consumption using Xilinx .