Low Power Design Of Carry Look Ahead Adder BY USING ADIABATIC LOGIC - Tilak Raju Daram,B.Navya Sri,. D.Indhuja, G.Manisha,A.Kavita Rao (International Journal of Advanced Science and Technology, 2020)
Now-a-days low power circuits play a major role in order to design a low power VLSI Circuits. Adiabatic circuits describe about the reversible logic i.e, it reuse the same, so through that the power has been saved. In conventional method, CMOS Circuits are been used to reduce the power dissipation in circuits. In order to overcome the drawback of the CMOS Circuits several adiabatic technique came into existence that are used to reduce the power dissipation further by charging and discharging. The techniques used are ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic logic). Full adders are used in Arithmetic Operation such as adder, multiplier etc. The Carry Look a Head Adder is also plays an important role by reducing the amount of delay in circuits and Carry Look a Head Adder is also known as FAST ADDER. Delay is one of the considerable in LOW POWER VLSI CIRCUITS and thus by using adiabatic technique the Power Dissipation in Full adder is reduced and by comparing ECRL and PFAL the power dissipation is reduced in both but slightly it is more reduced in PFAL. All the circuits are been simulated by using 130 nm technology using Software of Mentor Graphics EDA tool .