Power Efficient Control Unit Design Using 40nm Field Programmable Gate Array - Vidhu Baggan, Srishti Priya Chaturvedi, Aryan Kaushik (International Journal of Advanced Science and Technology, 2019)
In today’s modern generation, people are living in a digital world where each and every thing is interconnected and communicating. This generation is living in a technology dependent world. With the enlargement of population, the resources of energy are reducing. Therefore, there is a demand of developing efficient systems. Energy efficiency is a major concern and an active research area now a day. Therefore, this paper introduces an energy efficient Control Unit Circuit implemented with Field Programmable Gate Array (FPGA) Virtex-6 and Input/output Standard This research work has not only considered the transmitted power at every transmission node but also examined the consumed processing power on every reception node to analyze the overall performance of the circuit. This CU circuit is capable enough to perform its fundamental task with low power consumption. This research work has utilized FPGA, along with the I/O Standard and found that the power consumption level for the CU of a computer’s Central Processing Unit (CPU) has reduced significantly and furthermore, Stub Series Terminated Logic (SSTL) I/O Standard has been used for input and output power matching. FPGA is known for itshigh cost but based on the previous research work, it is also observed to be an efficient circuit. This work used a complete family of I/O Standard and each member’sperformance has been observed very carefully. For the coding purpose Very High Speed Integrated Circuit Hardware Description Language (VHDL) is used which is also an easy language and widely used. Simulation is performed on Xilinx ISE Design Suite and performance of the complete circuit is analyzed on X-power analyzer tool. After implementation, it is observed that the CU circuit using SSTL15 I/O Standard has consumed the least input power while on the contrary the circuit using SSTL2_II_DCI I/O Standard has utilized the highest power consumption. Keywords—FPGA, CU, SSTL I/O Standard, VHDL, Xilinx- Suite, X-power Analyzer.