Design and Implementation of High Speed, Low Power Vedic Multiplier - Vasudha V.Patil, Anil J. iPatil, Krupal P. Pawar (International Journal of Advanced Science and Technology, 2020)
Multipliers iare ivital icomponents iof iany iprocessor ior icomputing imachine. iMore ioften ithan inot, ithe iperformance iof imicrocontrollers iand idigital isignal iprocessors iare ievaluated ibased ion ithe inumber iof imultiplications iperformed iin iunit itime. iHence ibetter imultiplier iarchitectures iare ibound ito iincrease ithe iefficiency iof ithe isystem. iThe ivedic imultiplier iis ione isuch ipromising isolution. iIts isimple iarchitecture icoupled iwith iincreased ispeed iforms ian iunparalleled icombination ifor iserving iany icomplex imultiplication icomputations. iTagged iwith ithese ihighlights, iimplementing ithis iwith ireversible ilogic ifurther ireduces ipower idissipation. iPower idissipation iis ianother iimportant iconstraint iin ian iembedded isystem ithat icannot ibe ineglected. iThe igoal iof ithis iwork iis ito idesign ithe imultiplier iwhose ibase iis ian iAncient iIndian iVedic iMathematics iand iimplement iit iusing iReversible iLogic iand itest iit ifor iimprovement iin ithe icharacteristics iof imultiplier ilike idelay, ithe ipower iconsumption iof ilogical icircuit iusing iXilinx iISE itool. iSo ihere ithe iproposed imultiplier iis i"Vedic imultiplier iusing ireversible ilogic igate". Keywords: iVedic iMultiplier, iReversible iLogic, iUrdhva iTiryakbhayam, iQuantum iCost, ipower, idelay. i