FPGA Hardware Co-Simulation of DCSK Based on Bit-Flipping LDPC Decoding Using Xilinx System Generator - Mahmood F. Mosleh, Fadhil S. Hasan, Aya H. Abdulhameed (International Journal of Advanced Science and Technology, 2020)
Spread spectrum (SS) communications have accumulated interest due to their immunity to channel attenuation and low probability of intercept. Chaotic communication is the analog alternative of digital SS systems besides some extra features like simple transceiver structures. In this brief, Differential Chaos Shift Keying (DCSK)systems, non-periodic and random characteristics of chaos carriers and their interaction with soft info, are designed based on low density parity check (LDPC) codes. Due to simple structure and glorious error-correction capability. We evaluate the hardware performance and resource requirement trends of DCSK communication system based on the Bit-Flipping (BF) LDPC decoding algorithm over AWGN channel using the Xilinx Spartan-6 xc6sIx45t-fgg484 FPGA development kit. The results show that the proposed system has significant improvement in bit error rate (BER) performance and real time process. With much fewer amount of FPGA resources. The implemented system can achieve a BER performance of 10-4 at associate Eb/No of 3 dB. Keywords: DCSK, LDPC, BF decoder, Xilinx SG, Hardware co-simulation.