Design of Area Efficient and Low Power 16-Bit Hybrid MAC Unit using Vedic Mathematics

Abstract

Multiply and Accumulate (MAC) Unit is one of the vital operations used extensively in signal processing applications. Multiplier is the basic element of Digital Signal Processor (DSP). Power consumption, utilization of Look up Tables (LUT’s) and execution time parameters are decides the DSP performance. Thus, there is a need to design a low power, high speed and area efficient multiplier. In this paper, hybrid 16-bit MAC unit is designed using hybrid Vedic Urdhva Tiryakbhayam (UT) multiplier and conventional carry save adder. Comparisons among all the 16-bit MAC unit designs using existing both conventional Vedic UT and reversible Vedic UT multipliers are presented. The entire MAC units are designed and implemented using Verilog HDL. Further, simulation, synthesis and post-implementation was done using Xilinx Vivado design suite. The proposed hybrid 16-bit MAC unit design achieves significant reduction in power. In addition, a reduction in area 5.6% is achieved as compared with conventional and reduction of 13.05% area as compared with reversible 16-bit MAC unit designs.