Implementation of Frequency Efficient Multiplexer based CORDIC on FPGA
CORDIC (COordinate Rotation DIgital Computer) is the basic building block to generate trigonometric functions along with the design features such as reduced power, size and high speed for VLSI implementation. The major issue in CORDIC is its latency due to more number of iterations .Therefore, the computation speed is limited by the iterations or clock speed. In this paper, a modified multiplexer based CORDIC processor using pipelined Brent Kung Adder(BKA) based architecture is discussed. The approach efficacy has been understood on FPGA implementation. Here a CORDIC of sixteen bit for producing the trigonometric values is put into effect by two schemes; one is multiplexer based CORDIC using Ripple carry adder(RCA) and second is multiplexer based CORDIC using pipelined BKA schemes on both Xilinx Virtex 5 FPGA. It is observed from the synthesis results that the nonpipelined mux based CORDIC using pipelined BKA operated 10 times higher frequency than the nonpipelined multiplexer based CORDIC using RCA.