HIGH SPEED DYNAMIC SHIFT REGISTER FOR CONVOLUTION ENCODING AND VITERBI DECODING
The Convolution Encoder and viterbi decryption is displayed in this paper, which will be useful for high-speed applications. While encoding and decrypting bits, bits may need to be moved either left or right. Increase timing and complexity as we perform the variable action with more bits. To overcome this we suggest the dynamic transformation function of convolution encoding and viterbi decoding. The proposed shift register shifts four bits at a time. Execution is for the code rate of 1/2, the length of the constraint 9 and the implementation of the viterbi algorithm uses the Hamming distance instead of the Euclidean distance. Using the Hamming distance reduces the complexity of the system. The proposed architecture reduces energy consumption by approximately 51% when compares with the normal shift register. The code is written in verilog HDL and synthesized in Xilinx ISE tool.