Efficient Reversible adder architecture based on 45nm technology

Abstract

The aim of this paper is to a design of a low power efficient adder circuits using reversible logic gates. In this paper, four digital adders are designed using reversible logic gates. In general adders are the building blocks of arithmetic and logic unit, the design is based on the parameters like delay, power, area and number of gates. The main objective of using reversible logic is to avoid information loss and reduce heat dissipation. A newly designed reversible gate called SMG gate is used to design all four adders. The SMG gate itself will act as a full adder if its third input is made to zero. The required codes for the implementation of Adders are written in Verilog HDL. The circuits are simulated and synthesized in Cadence Virtuoso software. The proposed design is compared with existing one’s in terms of delay, power required, and area utilized.