TIMING ERROR AVOIDANCE TECHNIQUE USING TIMING CHECKER FLIP-FLOP UNIT FOR HIGH PERFORMANCE DESIGNS
The highest tolerable range in which the system operates properly is traditionally calculated based on the delays of the circuit's most long paths (known as critical paths). They can dominate the selection of critical paths in a manufactured chip and shorten an already short period owing to decreased gate delays. The timing error resilience is usually accomplished by tolerance circuit by consuming more power, area that leads to unavoidable overhead on the chip. The presence of more quantity of critical paths makes the layout intensifies such overheads. In this article, a timing margin for chosen critical paths is improved to create it robust against method and environment changes by using Timing error avoidance technique to adjust clock frequency. The Timing Error is scaled with the assistance of a time-checker flip-flop for high-design schemes.