Implementation of High Performance FFT Architecture for DSP Applications

Abstract

The wireless communication system requires high performance and low power implementation.  The core block in the communication systems is the Fast Fourier Transform (FFT), which is the crucial core of all modulators. The usage of FFT in real time application is limited by the cost and complexity of the hardware.  New techniques and approaches are required at all levels of design abstractions as future technologies are expected to provide unprecedented levels of computations performance in small hands-held units.  There are various method to implement FFT architecture. Canonic signed digit (CSD) algorithm, bit slicing architecture and the proposed architecture. The proposed design optimizing logic level and the active silicon area and speed are focused to compromise for the ASIC implementation.  The hardware implementation of the proposed FFT processor has 16-bit word length. This paper compares the different implementation using FPGA ASIC design for radix 2 butterfly architecture. The Experimental result indicates that the suggested architectures decrease the hardware cost considerably with respect to former implementation.  The proposed architecture having 10.6 % performance improvement.