Design and Analysis of Low Power High Speed Combinational Multiplier and Wallace Tree Multiplier for Image Compression

Abstract

Low power consumption and smaller area are some of the most important criteria for the fabrication of DIP (Digital Image Processing) systems and high performance systems. Since multiplication is an essential arithmetic operation for these applications. The area and speed of the multiplier is an important issue, increment in speed results in large area consumption and vice versa. In our project we try to determine the best solution to this problem by comparing a few multipliers. Power dissipation of integrated circuits is a major concern for VLSI circuit designers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. Multipliers play vital role in most of the high performance systems. This system depends to a great extent on the performance of multiplier thus multipliers should be fast and consume less area. This idea forced us to study and review about the multiplier. The result helps us to make a proper choice of different multipliers in fabricating in different arithmetic units as well as making a choice among different adders in different digital applications according to requirements. In addition, results from an image processing application demonstrate that the quality of the processed images can be controlled by the proposed multiplier design.

Keyword: Combinational multiplier, Wallace tree multiplier, adders, digital image processing.