Improvement in Computational Latency and Performance of Pipelined Interval Arithmetic Cordic Algorithm

Abstract

Abstract: Very large scale integration made a rapid advance in the research area of DSP in terms of high speed Very Large Scale Integration architecture for real time applications. Numerically intensive calculations are required for real scientific computations. In these calculations round off errors and catastrophic cancellation errors occur that leads to inaccurate results. In order to control the round off errors and catastrophic cancellation errors interval arithmetic techniques are used which do not use fixed values but uses an interval of values to ensure that the correct value lies within the limits of that interval only. Thus the efficient tool for monitoring errors is the interval arithmetic method. We propose pipelined interval arithmetic CORDIC architectures to efficiently support and identify the accuracy to accomplish interval trigonometric functions and to guarantee the correct possible option of the bounds of the final value with minimum error for the use of DSP (Digital signal processing) applications. This paper presents pipelined interval arithmetic Cordic algorithm for improvement in computational latency and performance of how it works and its implementation using MATLAB toolbox INTLAB. The outcomes show that the proposed algorithm provides reduction in computational latency and improvement in performance.