Modulo Ling Adder for high speed DA-RNS system

  • Shaheen Khan et. al

Abstract

In DA-RNS system, modulo addition is the main performance deciding operation. Therefore, in this paper, focus is made on the modulo adder part. For high-speed operation, all the input bits are processed at a time (ABAAT). The DA-RNS architecture uses the Binary Code (BC) for input and output representation while LUTs (Look-up Tables) avoid its logic complexity arising due to 2k modulo operation. The alternative existing shifter based approaches use Thermometer Code (TC) at any of the input or output stage or both. Although these techniques provide simple modulo accumulator circuit but also results in degradation of performance parameters as modulo size increases. The sum of product computation is validated for correctness and its performance is verified by designing and implementing a FIR filter for n=3, 4 and 5-bit operands mod adders. The Modulo Adder part of the filter circuit uses the hardware sharing concept for proposed Ladner Fischer Parallel Prefix Modulo Ling Adder (LFPPMLA). It is observed from Area-Delay-Power Product results that the proposed LFPPMLA based filter implementation experiment largely outperforms existing shifter based mod adder experiments.

Published
2020-02-02
How to Cite
et. al, S. K. (2020). Modulo Ling Adder for high speed DA-RNS system. International Journal of Advanced Science and Technology, 29(04), 582 - 596. Retrieved from http://sersc.org/journals/index.php/IJAST/article/view/4626