A Heuristic Technique for Architectural Realization Targeting 3D-Integrated Circuits

Abstract

A great deal of scaling of CMOS technology over the last three decades has enabled the realization of deep submicron VLSI circuits with billions of transistors on a single silicon chip. However, as minimum feature sizes reach lower than 10 nm, this rapid shrinking of CMOS scaling faces realization challenges associated with semiconductor fabrication, intercommunication delays, power, and energy dissipation. The three-dimensional (3D) approach of VLSI integration circuits (ICs) is a target technology that is used to deal with some of the challenges in the current technology of CMOS-integrated circuits such as number of through-silicon via (TSV) for which, in this paper, we present a heuristic scheme to optimize them. The input of our proposed approach is a data flow graph representing some digital signal processing algorithms that will be stored as list of equations, and the output is a minimized number of TSVs. The proposed scheme targeting 3D VLSI architecture is divided into phases (high-level-syntheses): scheduling, allocation and recourse binding, and layer assignment aimed at optimizing the number of TSV, taking into consideration power per control step in the time schedule. The proposed heuristic scheme is applied to some well-known DSP algorithms and is shown to produce good results compared to those from the conventional approach, in which a very intensive computational time approach (NP-complete), namely, the integer linear programming, is incorporated.