Design and verification of Discrete Time 3rd Order cascaded (2-1) Sigma Delta Modulator

Abstract

Analog communication technology has dominated the field of signal processing over a long period. However, nowadays, digital communication is playing a pivotal role in signal processing and manipulation, making the results more accurate, noise immune, and overall a stronger technique. The requirement of most efficient solution to digitize very diverse type of signals from ultra-low power biomedical to ultra-wideband communications is increasing in number of application scenarios. The systematic design of a 3rd order Sigma Delta (∑∆) modulator is described in Simsides, a time domain simulator with high accuracy and computational efficiency. The signal-to-noise ration and signal-to-noise plus distortion ratio of cascaded 2-1 modulator topology is improved when compared to the first and higher order modulators with proposed design parameters, integrator weights and over sampling ratio (OSR). The modulator designed using discrete time (DT) circuit technique with multistage noise shaping with 1-bit quantizer to avoid multilevel Digital to analog converter (DAC). The maximum SNR achieved in this modulator measured as 101.72 dB with effective number of bits 16.6 with high OSR. The ∑∆ modulator which is designed to be used for biomedical signals processing like ECG signals with achieved maximum resolution.