Design Of Accurate And High Precision Novel Fault Tolerant FFT

Abstract

The high speed Novel fault tolerant FFT design is proposed in this paper. Basically the FFT supports the bit size which is suitable to the system and mostly used in the long term evolution systems. Transport triggered architecture is utilized to customize the size of fault free FFT processor. Here the both energy-efficiency and performance is evaluated by using the standard cell technology. Address generation unit generates the address to access the main memory. The main intent of radix butterfly unit is to direct the rotations of system. Razor flip flop will detect and correct the errors occurred in the system. The fault free FFT processor system is programmable but shows energy-efficiency comparable to fixed-function ASIC implementations.