High Speed and MOSFET Reduction Based 24t Adder for Multiplier Design

Abstract

 The main intent of this paper is to design and implementation of 24T adder for Multiplier design at high speed and low cost. Basically, the implementation of 4*4 Multiplier is based in VLSI chips because they are used as critical element. In the same way arithmetic unit is used in the multiplier to perform the arithmetic operations. While designing arithmetic unit, optimized multipliers are used most widely. The 4*4 Multiplier uses adequate hardware implementation. The transistor logic system only depends on the 4*4 Multiplier to reduce the delay. Hence compared to adder system, the 4*4 Multiplier systems gives effective results in terms of speed, area and delay.