Analysis and Comparison of Finfet and Gnrfet based 14t Sram Cell with 10t and 12t Sram Cells

Abstract

With advent of portable devices there is a constant need to improve the performance of the device, for this SRAM cells are being used in System on Chipto reduce the memory access time. Since a significant amount of area in the System on Chip is used up by memory, optimization of SRAM cells is being researched.As the size of transistors is further reduced to pack more transistors in a unit of area, this can cause problems like idle state leakage current, difficulty to control transistor gate, limitation in oxide thickness etc. which can make it harder to design an efficient electronic circuit. Due to the problems faced in transistor size reduction, various studies are being done to solve the problems faced in nanometer range transistor design and develop superior materials for transistors to withstand and overcome the issues faced bygate lengths in terms nanometer. In process of finding new materials for transistors, FinFET and GNRFET are being developed which have better reliability and power efficiency than CMOS technology at nanometer range.