VLSI Implementation of Block Matching Motion Estimation Algorithm

Abstract

This paper proposes a parallel architecture for a successive elimination algorithm (SEA), which is used in block matching motion estimation. SEA effectively eliminates the search points within the search window and thus decreases the number of matching evaluation instances that require very intensive computations compared to the standard full search algorithm (FSA). The proposed architecture for SEA decreases the time to calculate the motion vector by 57 percent compared to FSA. The performance while applying the SEA to several standard video clips has been shown to be same compared to the standard FSA. The proposed architecture uses 16 processing elements accompanied with use of intelligent data arrangement and memory configuration. A technique for reducing external memory accesses has also been developed. A register-transfer level implementation as well as simulation results on benchmark video clips are presented. Comparison of design statistics on area and power between SEA and FSA implementations are also provided.