A High Speed Area Efficient Design of Kogge Stone Adder Using ZFC

Abstract

In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The study of conventional methods are studied those are ripple carry adder and carry look ahead adder. The ripple carry adder performs the addition operation by using two N-bit numbers and this process performs fast but the main dis-advantage of the ripple carry adder is that the carry bits have to wait for some time when performing the addition operation. Hence to overcome the delay by using kogge stone adder using ZFC logic is introduced. Generally, kogge stone adder is obtained from the family of parallel prefix adder. Hence this system is widely used in the arithmetic circuits which give high performance. Here all the carries are computed in parallel form to get low delay and occupy less area.