Low Area and Reduced Delay of Encoded Data Using Modified Bwar

Abstract

In current scenario, there are situations in a computing system where incoming information needs to be compared with a piece of stored data to locate the matching entry. Comparison of data is a technique which fetches data together from various sources and compares it. When this matching differs the stored data, the use of proprietary matching algorithms is used to compare and correct the mismatch result. As per the survey, different researches have been done and still going on till date. In this paper, a new architecture to reduce complexity and latency for matching the data protected with an error-correcting code (ECC). It is based on the fact that the code word of an ECC generated by encoding is usually represented in a systematic form, and it consists of the raw data and the parity information. The proposed architecture parallelizes the comparison of the data and that of the parity information. Furthermore, in a renovated butterfly weighted accumulator (BWAR), a type of reversible logic gate called PERES gate is proposed to modify the half adder with disparate algorithm to compute hamming distance with reduced complexity and improved efficiency with testable feature. The proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are correct.