Low-Power and Area-Efficient Shift Register Based on Decoder Enabled Pulse Generator

Abstract

This paper suggests a low-power, area-efficient 16-bit shift register with pulse generators powered by a decoder. Replacing flip-flops with casing with pulsed latches reduces surface area and power consumption. This method solves the timing problem between pulsating latches with pulsed clock signals that are much later than each other than the traditional single pulse clock signal. The shift register uses the number of pulsating clock signals by compiling latches for multiple sub-shift registers and adding multiple storage latches. Power consumption at 1000MHz clock frequency is 104mW. Compared the existing 16-bit shift register to the proposed 16-bit shift register, area consumption is reduced by 73 percent and power consumption by 19.3 percent.