A Study on Digitalized Forward-End Structure for ECG Realization Structure with Power Line Supply

Abstract

This design architecture defines a new approach for power line Electrocardiogram (ECG) signal realization system, that employed a entirely digital structural design to overcome the chip area and power consumption as well. The constructed structural design is compactable with digital CMOS technique. It is built up of in commission through a small amount of supply voltage range with 0.5 V. In this design approach, there is no correspondent building block, as example: coupling capacitors filters, no-inactive elements, low-noise amplifier (LNA) are used. There is a affecting standard of voltage-to-time converters are used. Those are behaving to carry on the LNA and anti-aliasing filter. A feedback loop in digital form is working to release the collision of the DC equalize on the route. It eliminates the requirement of coupling capacitors. The circuit is applied in the 0.18 µm CMOS technology. The management in which results demonstrate that the front-end circuit ingests 274 nW of power. The IECG signal, from 50 Hz to 100 Hz, is initially stressed by a band-pass filter. Accordingly, the output signal of the filter is transformed keen on a existing by a non-linear trans-conductance (Gm) cell.