Standby Mode Leakage PowerReduction Using VLSI Circuits

Abstract

In Low Power VLSI era, the Leakage Power is drawing a lot of attention ofthe VLSI IC designers in nanometer technology, due toitsprofound wastage of power.  It is necessary to rectifythe power wastage. There are Exact and Heuristic algorithms which are used to reduce the leakage power.

In this paper, a low leakage arithmetic logic unit is designed by constructing test circuits using single input NAND gate.   

Gravitational Search Algorithm is a stochastic Heuristic model, which locates the Minimum Leakage Vector (MLV). Then, by using the Input Vector Control (IVC) method, leakage power is minimized.  As a result, the wastage of power with IVC based GSA is controlled to only 1%.   

The comparative study is carried out with 3-input NAND gates of different models.  Test circuits of ALU are designedby PSPICE software and by using the IVC based GSA model,the leakage power is minimized.Xilinx 14.2 software tool with Verilog programming language is used to obtain the results.