Power and Area Constrained VLSI Implementation of Viterbi Decoder for High-Speed Communication Systems

Abstract

Due to the rapid growth in communication engineering, the implementation of encoder and decoder for real-time systems has more demands in the market.  Viterbi Decoder is a widely used decoding technique for converted encrypted data. The proposed design is compared with other traditional Viterbi decoding structures. Here, a low power carrier is used in addition to the selected combination of hamming distance calculators. The proposed design is implemented in FPGAs and specialized integrated circuits (ASIC). Convolutional encryption is one of the key-encryption schemes used in communication systems to execute the error correction code. The design packed in TSMC180nm and 45nm for performance. In this work, a new architecture of a user-programmable gate array (FPGA) is proposed to reduce power consumption and project distribution. It is found that around 5% of area and 7% power reduction is done when compared to the existing architecture.