Hardware Implementation of FIR Filters using FPGA

Abstract

Nowadays, the design and cost-effective hardware implementation of FIR filters is a challenging issue. Therefore, it would be necessary to find optimal filter coefficients to meet the passband and stopband requirements. This research work mainly focus on Canonical Signed Digit (CSD) based implementation of FIR filter on FPGA with fewer hardware components by employing only Adders/Subtractors as an alternative of using multipliers to achieve low latency and low power operations in wireless RF receivers. Modified low power Carry Select Adder (CSLA) using Look up Table (LUT) is used to perform addition operations to get higher performance in terms of speed and hardware resource utilization. First, the digital Farrow structure-based FIR filter is designed by combining Brain Strom Optimization (BSO) with Artificial Bee Colony (ABC) algorithm known as BSABC. Secondly, the designed filter is implemented in a Xilinx ISE environment in real time. The performance of this designed filter is compared in terms of delay, the number of LUT’s used with various other evolutionary algorithms such as Particle Swarm Optimization (PSO) and ABC. Moreover, the comparative analysis of the implementation based on Common Subexpression Elimination (CSE) and Multiplier Block (MB) method is also studied. It is observed that this approach simplifies the hardware implementation and achieves a reduction rate of about 28% in the number of LUT’s used.