Design and Implementation of Reverse-DCSK Communication System Using FPGA Technique

Abstract

In this paper, a reverse differential chaos shift-keying (RE-DCSK) communication system is implemented using Xilinx System Generator (XSG) tools. RE-DCSK system has high data rate and better security compared with DCSK system with the same bandwidth. In this system, the time inverse unit is used to generate an orthogonal basis of the chaotic signal to carry extra bit with small cost of complexity, where only one reference signal is transmitted for both information-bearing signals and this may be considered as equivalent to two DCSK systems. The theoretical bit error rate (BER) expression is analyzed over additive white Gaussian noise (AWGN) channel.  The FPGA hardware co-simulation of RE-DCSK system is developed using FPGA SP605 xc6slx45t-3fgg484 evaluation board with clock frequency 27 MHZ.