Optimized Even/Odd Parity Generator/Checker Circuits with Reversible Logic Approach

Abstract

Digital data transmissionis among the vital part of information access and process now-a-days. Moreover, error-free data transmission is required to be performed from source to destination devices on regular basis. Even/Odd parity Generators/Checkers are utilized to realize error-free communication between devices. Further, reversible logic approach designs low power loss circuits and systems. Here, we have presented three approaches for the reversible realization of Even/Odd parity Generator/Checker circuits. Proposed designs have been also analysed and compared with earlier designs. The optimization and comparison for these circuits have been made on total gates, garbage outputs and quantum cost etc. moreover, the suggested optimized approach has been synthesized and simulated for Xilinx software and ModelSim simulator respectively.