Design of Low-Power and High-Performance Wallace Tree Multiplier with Full Adder Modification

Abstract

High performance and low power design are a critical factor to be considered in designing any VLSI circuit.  Multiplier is one of the significant blocks in the design of any DSP application. In this paper, modification is done for the full adder present in the phase of reduction of Wallace multiplier.  The proposed modification of adder in this paper shows the improvement in power and performance(delay) of the multiplier design. The multiplier designs are generated by Verilog HDL. The functional verification is done using Xilinx Vivado and designs are synthesised in Cadence RTL Complier at 90nm CMOS technology. The synthesised results show the improvement in the performance of the multiplier.