Design and Analysis of a High Speed CMOS 12-bit 400-MSample/s using Switched Capacitive Flip around Technique for Pipeline ADC

Abstract

In today’s VLSI systems, increase in speed of analog and mixed-signal circuit design has emerged as a crucial challenge. This paper describes the design of 12-bit 400 MS/s pipeline Analog-to-Digital converter (ADC) for high speed applications. In the pipeline ADC design is mainly focused on resolution and high speed to meet various applications. The advantage of pipeline technique is simple to implement, easy to design layout and have flexibility to improve in speed. A proposed technique includes an operational transconductance amplifier (OTA), sample and hold circuit (S/H), comparator and multiplying DAC to implement the pipeline ADC. A switched capacitor integrator module is used to convert differential input voltage into current through OTA. A S/H circuit is incorporated in the initial stage of a pipeline design, which removes a dedicated S/H amplifier. Simulation result shows that the ADC has achieved a maximum differential and integral nonlinearities are +0.48/-0.55 LSB and +0.61/-0.75 LSB, respectively. Signal to noise dynamic range (SNDR) obtained is 64.2dB and a spurious free dynamic range (SFDR) of 81.8dB. At transistor level each block is designed, simulated and verified using Cadence EDA tool with 45nm technology on analog design platform.