Design Of High Speed And Reduced Hardware Complexity Alu Using Hybrid Kogge Stone Adder

Abstract

The adders, multipliers are the essential building blocks for every integrated circuit(IC) and  especially for Arithmetic and Logical units(ALU).Thus, the  design of adders and multipliers must inhibits the area, delay and power efficient properties. But most of the conventional adders are failed to provide these properties in multipliers and ALUs implementation. To solve this problem Hybrid Koggestone adder (HKSA) has been developed at nano technology level using the parallel prefix addition (PPA) properties. The quantum cost for this HKSA is very low, thus in this paper HKSA based N-bit adder, N-bit subtractor, N-bit multiplier and N-bit ALU developed with reconfigurable properties. The effective utilization of the HKSA provides more flexible nature for ICs. The implementations are conducted in Xilinx ISE environment, the simulation results shows that proposed method is area, power and delay efficient compared to the conventional approaches.