A Review on Power Reduction Techniques in Low Power VLSI Design

Abstract

The paper investigates different techniques used for the reduction of power in VLSI design at different levels of abstraction.
The field of computing devices and wireless communication system seamlessly requires the ability to perform complex functionality with higher computation speed and with minimal power consumption. Hence, recent VLSI designs mainly focus on optimizing speed and computation ability, which automatically inherit the power dissipation in the form of dynamic power dissipation and leakage power. These powers are an important fraction of the total power dissipation of integrated circuits. Many cogent power reduction techniques are surveyed which involve reducing dynamic power using supply voltage reduction, reduction of threshold voltage, various power gating techniques.
This paper also includes future challenges the blend of traditional and present power reduction techniques.