Efficient Composite Physically Unclonable Function Architecture for Enhancing FPGA Security

Abstract

Background/Objectives: In this paper, the hardware design of a Composite PUF (C-PUF) architecture to enhances the robustness, tamper-sensitivityand reliability single-use and primitive PUFs architectures for securing FPGAdevices is presented.

Methods/Statistical analysis: The core architecture consistsof SRAM, for implementing the SRAM-PUF and the Ring Oscillator. These two primitive PUFs are used as the building blocks to constructing the proposed Composite-PUF architecture.  This proposed architecturereveals an improvement in thereliability and uniqueness: - the main statistical measure of the quality of a PUF. The architecture was modeledand simulated with Verilog HDL and Modelsim SE Integrated Development Environment tools.

Findings: Silicon-based random functions that depend on the physical properties of the silicon manufacturing process, also known as Physically Unclonable Functions (PUF), provide primitives based on challenge-response pairs. These PUFs in conjunction with certain lightweight block and stream ciphers are some of the means of securing these devices holistically. The forms of hardware attacks get varied and sophisticated with each passing time especially with the availability of higher computing power and other forms of advanced technologies. This presupposes that there are still attacks that can be or are being leveled against some of these PUFs.This research proposes a composite-PUF architecture that is complex, possess a high degree of reliability and uniqueness and is equally highly suitable and easily implemented on FPGAs to enhance their security.  The proposed architecture was designed using both the Xilinx ISE and Vivado tools. The resulting architecture was synthesized using synopsis’ design compiler (DC) and Xilinx Synthesis Tool (XST) 14.7.

Improvements/Applications: Theproposed Composite-PUF architecturewas implemented on 3 Spartan-6-FGG484 Field Programmable Gate Arrays (FPGA) with experimental results showing the proposed architecture had a uniqueness of 49.63% and is 98.19% reliable. 

Keywords: Physically UnclonableFunctions, Ring Oscillator, Challenge-Response-Pair, FPGA, Hardware Security, SRAM